In sum, SoC-ImP^® provides a predictable and derivative mechanism, which is composed of systematic process, configurable script database, accumulated EDA tool experiences and Socle's own methodologies and expertise for the challenges of the UDSM era.

The complexity of a SoC design implementation has increased dramatically, not only on the choices of various EDA tools adoption and tremendous investment, but also on the trade-offs among different design aspects considering multiple IPs’ integration. The SoC-ImP^® technology is introduced to expedite customer’s EDA tool investment, engineering effort in tool integration as well as implementation and process technology demand.
Hence, in order to meet the customer’s schedule, performance and delivery quality requirements, Socle’s SoC-ImP^® implementation platform is constructed with a well-organized framework structure, systematic procedure and clean sign-off mechanism. Thus Socle has successfully tape out hundreds of projects on 90nm/130nm/180nm process technologies and helped many customers achieve mass production.

SoC Implementation Platform
SoC-ImP^® includes an optimized and pre-verified flow, which is constructed in a well-organized framework structure. The SoC-ImP^® is a hierarchical physical synthesis based design closure environment which integrates Lib/IP qualification, RTLDA, timing, DFT, power, reliability (signal integrity, EM/IR), physical design (place and route) solutions.

- Library & IP Qualification Solution – systematic and automatic ways to pre-qualify various foundry and customer IPs for difference foundries and processes.
- RTLDA Solution – qualifies the RTL code and finds the bug at an earlier stage, the cost is then lower and easier to fix with fewer resources and schedule.
- Timing Closure Solution – accelerates the timing convergence with architecture driven implementation and seamless integrated with couple implementation solution.
- Physical Design Solution – provides the UDSM technique and DFM rule fixing to improve the manufacturing yield.
- DFT Solution – enhances the test coverage on logical circuits, yield on memory and testability of the system.
- Power Closure Solution – provides accurate power analysis and optimizes power consumption to increase the battery life cycle for portable products.
- Reliability Closure Solution – reduces the signal net and power net noise to meet signal integrity and power net work integrity requirements.

SoC-ImP^® Process Controller Mechanism:
The SoC-ImP^® platform adopted the WBS (work-breakdown structure) project management mechanism with a comprehensive embedded phase/stage/task process controller.
- Phase: Major component within the project life cycle. Combine several stages to meet one milestone and define sign-off criteria with customer. There are two major phases in SoC-ImP^®.
RTL Prototype: Provides the predictable timing, CTS result, die size, power consumption, testable coverage and IR/EM reliability report.
Silicon Prototype: Provides the final chip implementation performance result, physical verification report to meet the tape out sign-off quality.
- Stage: WBS entry, combines several tasks to finish one stage objective. Like RTLDA is composed of code purification tasks
- Task: deliverables are assigned to an individual, combine procedures or process, which can invoke an EDA tool to execute the task.

Linux Server
1. 32bit x 5
(1 P4 CPU, 4G Mem)
2. 32bit x 2
(2 Xeon CPUs, 4G Mem)
3. 64bit x 4
(2 AMD CPUs, 8G Mem)
Total Linux = 11

Storage
1. EMC : 0.8T
2. HDS : 1T
Total capacity = 1.8T