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Introduction
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Platform2Silicon abridges the
design gap between the idea and physical prototyping and all the way
down to chip production services.
Socle Technology, the leading SoC design service company, has developed
a "Platform2Silicon"
service to optimize your SoC design, maximize the productivity of
your engineering and minimize the potential risk of your product.
Socle offers joint development with customer to construct the executable
specification, design integration, function verification and implementation.
To make your idea and concept to market on time is a key factor to
the success of a product and business profit. How to shorten the design
cycle and reduce the development cost is a big challenge in deep sub-
technology. Socle Technology provides you with the Platfrom2Silcion
solution to abridge the design gap between the specification and physical
prototyping and all the way down to chip production services.
The Platform2Silicon design service
is based on Socle's two key technologies -  Platform®
and SoC-ImP®.
Platform®
is a configurable and pre-verified MIPS/ARM based SoC platform which
provides the complete solution from Specification to RTL development.
SoC-ImP® is a systematic and pre-verified
implementation environment, which provides the RTL to silicon service,
the silicon will be GDSII, wafer or well tested chip. |
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Service Flow
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Socle Technology is proud of our service quality. We
guarantee your SoC by meeting both schedule target and performance
goals. The Platform2Silicon service flow is as Fig. 1. |
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Methodology
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 Platform®
design platform. Platform®
is a configurable and pre-verified SoC design platform. |
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Platform®
reusable verification platform. |
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Platform®
hardware evaluation board for hardware integration and software
development in the earlier SoC design verification. |
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Platform®
is tightly linked to Platform2Silicon design service.
More detail, refer to  Platform®
Technology |
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Deliverables
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Platform®
core netlist |
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Platform®
integration support |
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Platform®
verification testbench |
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Platform®
development evaluation board |
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Platform®
device drivers |
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Platform®
BSP for Embedded OS & RTOS |
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Platform®
training program |
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Platform®
integration guide/application notes |
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Diagnostic Program for Platform®
EVB |
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Boot Loader for Embedded OS |
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Environment
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Platform®
environment
| Hardware Design |
Verilog Simulator |
Synopsys: VCS
Mentor Graphics: ModelSim
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| Test Bench Generator |
Verisity: Specman |
| Debugger(Waveform Viewer |
SpringSoft: Debussy |
| Software Design |
Tool chain |
WindRiver: Tornado 2.0.x
GNU |
| OS |
WindRiver: VxWorks
Monta Vista: Embedded
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| ICE |
EPI, GreenHill |
| Hardware Prototyping |
FPGA Compiler |
Synplicity: Synplify Pro |
| FPGA P&R |
Altera: Quartus II
Xilinx: ISE 5.x
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| Evaluation Board |
MIPS/ARM CPU EVB
Socle Platform
EVB
AHB2PCI EVB
UDC 2.0 EVB (w/ PHY)
Ethernet MAC EVB |
SoC-ImP®
environment
| Design Methodology/Flow |
EDA Tools |
| Code Purification |
Synopsys : Nova-Explorer |
| Synthesis |
Synopsys : Design Compiler
Cadence : PKS |
| Physical Synthesis |
Synopsys : Physical Compiler
Cadence : PKS |
| Floorplan and P&R |
Cadence : FE
Synopsys : Astro |
| Layout Editor |
SpringSoft : Laker |
| RC Extraction & Central Delay Calculation |
Synopsys : Star-RCXT
Cadence/Celestry : MDC-SI |
| Layout Verification |
Mentor Graphics : Calibre |
| Static Verification |
Synopsys : PrimeTime
Verplex : LEC |
| Dynamic Verification |
Synopsys : VCS
Cadence : NC-Verilog
Mentor : Modelsim
SpringSoft : Debussy |
| DFT & ATPG |
Synopsys : DFT Compiler, TetraMAX
LogicVision : MBIST-IC, BSD |
| Power Analysis |
Synopsys : Power Compiler , Prime
Power
Cadence : Voltage Storm |
| Signal Integrity |
Cadence/Celestry : Nautilus
Synopsys : Astro Xtalk |
| Test Bench Generation |
Verisity : Specman |
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Request Form : |
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Please contact with our sales
representative |
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