To meet complex SoC design implementation requirements,
Socle introduces the Power Closure Solution to overcome those
frequently-encountered challenges see below, for a low power
SoC market trend.
How to provide accurate power analysis for chip
spec. confirmation and power plan in chip size reduction?
How to optimize dynamic power in order to increase the battery
life cycle?
How to optimize leakage power and increase the standby period?
With a Power Closure Solution derived from SoC-ImP
® technology, the more secure and comprehensive
integrated implementation platform solution shall be introduced
by Socle for a successful SoC customer.
Features
:
Fast and accurate power analysis in the early design cycle
Vector/Vector-less power analysis for RTL /Gate-level design
Detailed and comprehensive analysis at the later stages of the design cycle
Strongly link to reliability solution.
Reduce the leakage power with multiple Vt library and solution.
Dynamic power optimize with ICG (Integrated Clock Gating) cell.
Using the ICG solution to solve STA timing borrowing, CTS balance, clock glitch and DFT rule violation issue.
Benefits
:
Accurate power estimation to reduce the area
and meet reliability requirements
Simultaneous optimization for timing, power, area and scan based design
Low power approach enables longer standby period and battery
life cycle for portable products
