SOCLE TECHNOLOGY CORP.

Physical Design Solution

Introduction :

To meet complex SoC design implementation requirements, Socle introduces the Physical Design Solution to overcome those frequently-encountered challenges see below, for UDSM SoC design.
	How to strongly link timed closure, power grid analysis and signal integrity solutions?
	How to handle DFM related rules to avoid layout pattern variation resulting in metal damage caused decreases in chip yield?
	How to handle customized IP integration?
With Physical Design Solution derived from SoC-ImP ^® technology, a more secure and comprehensive integrated implementation platform solution shall be introduced by Socle for a successful SoC customer.

Features :


	Top down or bottom up hierarchical floorplan partition and placement.
	Hierarchical power plan with IR/EM analysis and fixing.
	SI prevention during global routing and fixing during detail routing.
	Global and local spare cell insertion for easy ECO and FIB support.
	Gated Clock Tree Synthesis and optimization
	3D RC extraction with SPEF output
	DCAP cell insertion to reduce ground bounce.
	Redundant VIA doubling and dummy metal filling for DFM.
	Hierarchical physical DRC/LVS/Antenna/Density/LVL verification.
	Fully link to Library IP Qualification solution.

Benefits :

Exercise experienced physical design engineering team that provided the complete solution for more complexity, higher performance, quality and design reliability
	Multi million gate count design with hierarchical flow support.
	Complete design flow and aggressive schedule to meet TTM (Time- to- Market).
	More compact chip area for competitive chip prices.
	Flexible ECO solutions for FIB fixed easy and Mask cost saving.
	DFM rule handling for manufacturability and yield improvement.

Support :

	Floor plan consultant support
	SIP merge guideline and integration support
	SIP merge support
	e-Job view support