SOCLE TECHNOLOGY CORP.

Leopard Solution

Introduction :

Socle Leopard solution intends to provide not only a flexible platform compiler (Leopard Core Compiler) approach technology.

To cope with customer SoC demand, the Leopard Core Compiler includes various AMBA based IP solutions, but also the fully integrated design and verification platform solution that was derived from the uPlatform tech to efficiently generate the required platform core set from silicon proven Leopard Core set. The Leopard Core adopts de facto 32-bit AMBA 2.0 single/multi-layer AHB bus(es) architecture with low latency memory controller, high performance I/O and peripherals, power management unit, high efficiency bus transfer and interruption controller. To further extend application needs, the Leopard Core could easily be extended with Socle's Media Solution and File System Solution.

The Leopard Core offers flexible AHB/APB bus expansion to integrate customer design IPs. A verification platform solution is also provided in order to ensure the design integrity and functionality from SoC point of view.

Features :

Static/SDRAM Memory controller
		SDRAM controller interfaces directly with AHB bus.
		Supports FLASH/SRAM/ROM/SDRAM access.
		Supports 1 independent slave port for register control, and up to 2 slave ports for data access.
		Dual write buffers for simultaneous write posting and SDRAM access by each AHB master.
		Dedicated read buffer with data width matching.
		Supports up to 4 Flash/ROM banks and up to 8 SDRAM banks.
		Early burst termination and AHB master busy are supported.
		Supports AHB bus data width of 8, 16 and 32 bits.
		Zero wait state burst data transfer on both AHB and SDRAM.
		Pipeline access allows continuous data transfer without wasted cycles.
		Fast page access on row address matching.
		Independent row address matching for each of the 4 SDRAM banks.
		Programmable SDRAM and static memory timing parameters.
		Automatic refresh generation with programmable refresh intervals.
DDR SDRAM Memory Controller
		DDR SDRAM controller interfaces directly with AHB bus.
		Supports DDR SDRAM access.
		Supports 1 independent slave port for register control, and up to 2 slave ports for data access.
		Dual write buffers for simultaneous write posting and DDR SDRAM access by each AHB master.
		Dedicated read buffer with data width matching.
		Supports up to DDR SDRAM banks.
		Early burst termination and AHB master busy are supported.
		Supports AHB bus data width of 8, 16 and 32 bits.
		Zero wait state burst data transfer on both AHB and DDR SDRAM.
		Pipeline access allows continuous data transfer without wasted cycles.
		Fast page access on row address matching.
		Independent row address matching for each of the 2 DDR SDRAM banks.
		Programmable DDR SDRAM timing parameters.
		Automatic refresh generation with programmable refresh intervals.
Static Memory Controller
		Static memory controller interfaces directly with AHB bus.
		Supports FLASH/ROM access.
		Supports 2 AHB interfaces, one for accessing memory and one for accessing control registers.
		Dedicated read buffer with data width matching.
		Supports up to 4 Flash/ROM banks.
		Programmable static memory timing parameters.
Interrupt Controller
		Provides 2-stage, 8-level programmable hardware priority interrupt resolution.
		Programmable rise/fall edge, high/low level interrupts source capability.
		Provide up to 32 interrupt sources service.
AHB Bus Arbiter
		Provide round robin, fixed parity programmable arbitration scheme.
		Provide 2-stage, 4-level programmable for fixed parity arbitration.
		Provide up to 16 AHB masters service.
AHB-to-PCI Host Bridge
		AHB to PCI bus protocol translation.
		Fully supports PCI specification 2.1 and 2.2 protocol.
		Downstream access allows AHB bus devices such as CPU to access PCI bus.
		Upstream access allows PCI bus devices to access system resources on AHB bus.
		Total of six write buffers for write data posting for all interfaces.
		Read access to PCI bus handled as delay read to prevent system deadlock.
		Generates standard PCI type0 and type1 configuration accesses.
		Supports early burst termination and CPU master busy.
		Automatic handling of configuration registers read/write access.
		Supports target retry, disconnect, abort and wait state insertion.
USB2.0 Device Controller
		Complies with the USB2.0, supports USB full speed and high speed and is backward compatible with USB1.1.
		Double buffering scheme for main endpoint increases throughput and eases real-time data transfer.
		Support up to 16 endpoints.
		Automatic retry of failed packets and PING Flow control.
		Separate data buffers for the SETUP portion of a CONTROL transfer.
		Provide DMA Engine for AHB data access.
10/100M Fast Ethernet MAC 0/1
		Meet IEEE 802.3 CSMA/CD standard.
		Media Independent Interface (MII).
		Support 10/100M bps transfer data rate.
		Support full or half duplex operation.
		Support up to 16 flexible physical address filtering, and 512-bit hash table for multicast address.
		Intelligent arbitration between transmits and receives process.
		Provide link list DMA engine for AHB data access.
		Support "ring" and "chain" types data buffering structure.
		Provide 2K-byte transmit FIFO and 2K-byte receive FIFO.
Test Interface Module (DCM)
		Provide AHB master interface, which can transfer external test vector to AHB bus for ATE.
		Low over-head test and debug interface.
SCU
		Provide system clock and reset control.
		Provide decoder REMAP function for ARM series processor.
GPIO
		Up to 32 individually programmable input/output pins.
Serial Peripheral Host Interface (SPI)
		Four transfer protocols available with selectable clock polarity and clock phase.
		Different bit rates available for SCLK.
		Support up to 8 slave devices.
		Full duplex synchronous serial data transfer.
I2C Master/Slave Interface
		Compatible with I2C specification v2.1.
		Support Master or Slave device mode of I2C bus.
		Support multi-master operation.
		Support 7-bit or 10-bit address mode operation.
		Programmable clock frequency and transfer rate up to 400Kbps
UART0 (16550)/IrDA SIR
		Programmable use for UART or IrDA SIR input/output.
		Separate transmit and receive FIFO buffers (16 x 8) to reduce CPU interrupts.
		Supports up to 115.2Kbps baud-rate for UART and 115.2Kbps half-duplex data rate for IrDA SIR.
		Programmable baud rate generator. This enables division of the internal clock by (1 ~ 65535 x 16) and generates an internal x16 clock.
		Standard asynchronous communication bits (start, stop and parity). These are added prior to transmission and removed on reception.
		Independent masking of transmit FIFO, receive FIFO, and receive timeout and error condition interrupts.
		False start bit detection.
		Line break generation and detection.
		Fully-programmable serial interface characteristics: - Data can be 5, 6, 7, 8 bits. - Even, odd, stick or no-parity bit generation and detection. - 1 or 2 stop bit generation. - Baud rate generation.
UART1 (16550)
		Separate transmit and receive FIFO buffers (16 x 8) to reduce CPU interrupts.
		Supports up to 115.2Kbps baud-rate.
		Programmable baud rate generator. This enables division of the internal clock by (1 ~ 65535 x 16) and generates an internal x16 clock.
		Standard asynchronous communication bits (start, stop and parity). These are added prior to transmission and removed on reception.
		Independent masking of transmit FIFO, receive FIFO, and receive timeout and error condition interrupts.
		False start bit detection.
		Line break generation and detection.
		Fully-programmable serial interface characteristics: - Data can be 5, 6, 7, 8 bits - Even, odd, stick or no-parity bit generation and detection. - 1 or 2 stop bit generation. - Baud rate generation.
Timer
		Built-in 3 32 bits timer modules.
		Provide independent free-running or periodical mode.
		Mask-able interrupt.
Watchdog Timer (WDT)
		Watchdog function.
		Built-in 32 bits programmable reset counter.
Real Time Clock (RTC)
		24-hour time mode with highest precision of tenth of a second.
		Calendar function with correction for leap year.
		Programmable alarm with interrupt generation.
		Mask-able interrupt.
AHB-to-APB Bridge
		AHB to APB bus protocol translation.
		Support byte, half word and word data transfer sizes.
		Support RETRY function to enhance AHB bus utilization.
Expansion Capability
		Support 8 AHB master expansion interface.
		Support 8 AHB slave expansion interface.
		Support 8 APB slave expansion interface.
		Support 21 external interrupt sources .

Benefits :

	Pre-verified Platform Core Compiler Solution to best fit customer SoC requirements
	Flexible Bus Expansion to Allow Customer Plug Their Design with Leopard SoC Easily
	Fully synthesizable RTL code and ready to target for world-class foundries and processes
	Silicon/System/Application Proven Leopard IP and Leopard enabled SoC

Supporting :

	Leopard Core maintenance
	Leopard Core design integration and verification support
	Leopard Core system integration with LDK support
	Leopard Core related training