DFT Closure Solution
	Introduction :   To meet complex SoC design implementation requirements, Socle introduces the DFT Closure Solution to overcome those frequently-encountered challenges see below, for a manufacture risk-free approach.   How to improve chip quality after testing?   How to reduce the cost of testing?   How to provide support for millions gate count SOC design DFT solution?   How to link DFT with timing closure solution? With the DFT Closure Solution derived from SoC-ImP ® technology, the more secure and comprehensive integrated implementation platform solution shall be introduced by Socle for a successful SoC customer.   Features :   Internal Scan & ATPG feature   Hierarchy DFT implementation.   DFT rule introduction and rule check.   DFT planning and one pass scan synthesis   Unified Design Rule Checker of Scan synthesis and ATPG engine   Auto test pattern generation and verification MBIST feature   Support the SRAM, Register File and ROM   Support SMarch algorithm   100% coverage of memory related faults   Support RTL/Gate-Level Netlist   Integrated with internal scan solution to reduce the share pins and enhance the testable coverage MBISR feature   1D spare row or 1D spare column and segment solution   2D spare row and column solution   Support March-CW MBIST and Must-Repair Algorithm   Soft Repair. BSD feature   Fully Compatibility with 1149.1   RTL/Gate-Level automation flow for fast test integration   Integrated with placement engine to reduce the timing side effect     Benefits :   Tightly integrate flow with timing closure for minimum interaction and timing impact between DFT and Timing closure. Selectable MBIST algorithms to meet high fault coverage test. Optimized 1D and 2D redundancy memory and repair solution for effective embedded memory yield improvement. Provide BSD for system level testing capability enhancement     Support :   DFT coding guideline training Test coverage improvement support