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DDR PHY Solutions / Memory IP


Overview

The DDR Memory Interface IP provides complete system-level IP solutions for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4, DDR3/3L, DDR2, LPDDR5, LPDDR4/4X, LPDDR3, LPDDR2, LPDDR, HBM2 and HBM2E SDRAMs or memory modules (DIMMs). Optimized for high data bandwidth, low power and enhanced signaling features, the complete DDR Memory Interface IP solution includes a choice of scalable digital controllers, an integrated hard macro PHY delivering memory system performance of up to 6400 Mbps, and verification IP. We provide several DDR PHY IP cores to choose from, as detailed in the table below.

Most of the DFI-compatible DDR PHYs are provided by our unique DDR PHY Compiler. The DDR5/4 Controller, LPDDR5/4/4X Controller, and Enhanced Universal DDR Memory and Protocol Controller IP feature a DFI-compliant interface, low latency and low gate count while offering high bandwidth. Optional market-specific features like AMBA AXI/4 AXI Quality of Service (QoS) and Reliability, Availability and Serviceability (RAS) features allow you to match the area and capabilities of the controllers to your needs.

In addition, Socle provides a complete HBM IP solution to meet the essential high-bandwidth and low-power memory requirements of high-performance computing, AI and graphics SoCs. 

Verification IP
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