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PLL


Overview

U40LPGPIOLEDV1 is a general purpose I/O with LED driving IP. It is based on UMC 40nm low power process.

Features
  • Process: UMC 40nm Logic and Mixed-Mode 2.5V/1.1V Low Power Process
  • Pill-up resistor: disable/2.2K/50K
  • Driving: 4mA/8mA/16mA/32mA
  • Pull-low enable
  • Output enable
  • IO enable
  • LED resistor 0/200/300/500
  • Power Supply:
    • IO power supply 3.3V
    • Core power supply 1.1V
    • Operated Ambient Temperature: Ta = -40 ~ 85°C
  • Area < 90um x 120um
Functional Pin Description
Functional Block Diagram


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