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DDR


Overview

The T40LP_DDR3TOPV01 IP is a high-speed interface for high-performance DDR3 PHY applications. This IP based on TSMC 40nm LP process. The operation speed is up to 800MHz (1600Mbps) at 1.5V voltage for DDR3 application. The on-die termination (ODT) is provided to improve the signal integrity (SI).

Features
  • Process: TSMC 40nm LP process
  • Support DDR3 1.5v
  • Various ODT values provided, Res : 20~100ohm
  • Various OCD values provided
  • Support internal Vref generation
  • Support internal PLL
  • Support wire bond and flip chip packaging
  • Operated Ambient Temperature: Ta = -40 ~ 85°C
  • Operated Junction Temperature: Tj = -40~125°C
Block Diagram


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