Socle has been delivering SoC design services(SoC-ImP®) by robust flow cover 0.25um to 7nm technology. SoC-ImP® methodology resolves the challenges of million gates by DFT, Power analysis, Placement & Routing, RC Extraction, Timing Analysis, IR Drop / Electro Migration, Design For Manufacturing (DFM), by time to market requirements.
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In Design-For-Testability (DFT) services, Socle delivers scan, boundary scan, memory BIST insertion, and provides scan re-ordering, low power test pattern generation and compression, fault coverage analysis services.
In Low power technique, SoC-ImP® integrate low power format(IEEE 1801/UPF/CPF), optimize DVFS(Dynamic Voltage Frequency Scaling), make leakage power saving up to 10X, dynamic power saving up to 20%. And also support clock gated design and Vt cell swap low power methodology.
In timing closure with MMMC(Multi Mode Multi Corner), and on chip variation (OCV) for multiple power domain/on-off domain verification.
SoC-ImP® flow proven by tablet, IP Cam, 8K TV Set-Top-Box, 5G, AI application…,ect. Over 500 projects